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TDA7442 TDA7442D
TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSOR
1

FEATURES
4 STEREO INPUTS INPUT ATTENUATION CONTROL IN 0.5dB STEP TREBLE AND BASS CONTROL TWO SURROUND MODE AVAILABLE WITH 4 SELECTABLE RESPONSES: - MUSIC - SIMULATED STEREO TWO SPEAKER ATTENUATORS: - 2 INDEPENDENT SPEAKER CONTROLS IN 1dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS 2 MONITOR OUTPUT (ONLY FOR TDA7442)
Figure 1. Packages
SO-28
SDIP-32
Table 1. Order Codes
Part Number TDA7442 TDA7442D TDA7442D013TR Package SDIP-32 SO-28 Tape & Reel

mable phase shifter. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the BIPOLAR/CMOS Technology used, Low Distortion, Low Noise and DC stepping are obtained.
2
DESCRIPTION
The TDA7442/42D is volume tone (bass and treble) balance (Left/Right) processors for quality audio applications in TV and Hi-Fi systems. It reproduces surround sound by using a programFigure 2. Pin Connections (Top views)
R-IN2 R_IN3 R_IN2 R_IN1 L_IN1 L_IN2 L_IN3 L_IN4 MUXOUTL IN(L) MUXOUT(R) IN(R) BIN(R) BOUT(R) BIN(L) 1 2 3 4 5 6 7 8 9 10 11 12 13 14
D98AU948
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D01AU1247
32 31 30 29 28 27 26
R-IN3 R-IN4 L-OUT R-OUT AGND VS CREF SDA SCL DIGGND TREBLE-R N.C. TREBLE-L PS1 LP BOUT(L)
28 27 26 25 24 23
R_IN4 LOUT ROUT AGND VS CREF SDA SCL DIG-GND TREBLE(R) TREBLE(L) PS1 LP BOUT(L)
R-IN1 MONITOR(L) MONITOR(R) L-IN1 L-IN2 L-IN3 L-IN4 MUXOUT(L) IN(L) MUXOUT(R) N.C. IN(R) BIN(R) BOUT(R) BIN(L)
SO28
22 21 20 19 18 17 16 15
SDIP32
25 24 23 22 21 20 19 18 17
June 2004
REV. 2 1/17
TDA7442 - TDA7442D
Figure 3. Block Diagram (TDA7442)
5.6nF 5.6K 100nF 100nF
100nF 2.2F IN(L)
MONITOR(L) 0.47F L-IN1 50K 0.47F L-IN2 50K 0.47F L-IN3 0.47F L-IN4 50K 7 50K 8 6 5 3
MUXOUT(L) 31.5dB control 9
PS1 19 RPS1
TREBLE-L 20 16
BIN(L) BOUT(L) 17 RB
10
FIX
30K PS1 90Hz OFF 79dB CONTROL VAR SPKR ATT MUTE -
+ + L+R
SYMULATED
MUSIC/ SYMULATED MUSIC MIXING AMP
FIX TREBLE BASS
+ 0.47F R-IN1 50K 0.47F R-IN2 50K 0.47F R-IN3 50K 0.47F R-IN4 50K 31 31.5dB control 4 MONITOR(R) 11 MUXOUT(R) 13 IN(R) 32 30K 1
L-R
OFF
2
I2C BUS DECODER + LATCHES
LPF 9KHz
EFFECT CONTROL
MIXING AMP SURR
TREBLE
BASS FIX VAR + SPKR ATT
OFF
SUPPLY
Vref RB 22 CREF TREBLE-R 14 BIN(R) 13 BOUT(R) D98AU947B
18 LP
27 VS 1.2nF
28 AGND
26
2.2F
22F 5.6nF 100nF 5.6K 100nF
Figure 4. Block Diagram (TDA7442D)
5.6nF 5.6K 100nF 100nF
100nF 2.2F IN(L)
MUXOUT(L) 0.47F L-IN1 50K 0.47F L-IN2 50K 0.47F L-IN3 0.47F L-IN4 50K 6 50K 7 + + 5 4 31.5dB control 8
PS1 17 RPS1
TREBLE-L 18 14
BIN(L) 15 RB
BOUT(L)
9
FIX
30K PS1 90Hz OFF 79dB CONTROL VAR SPKR ATT MUTE -
SYMULATED L+R MUSIC + L-R OFF
MUSIC/ SYMULATED MIXING AMP
FIX TREBLE BASS
0.47F R-IN1
3 50K
I2C BUS DECODER + LATCHES
0.47F R-IN2
2 50K
LPF 9KHz
EFFECT CONTROL
MIXING AMP SURR
TREBLE
BASS FIX VAR + SPKR ATT
0.47F R-IN3
1 50K 30K OFF
0.47F R-IN4
28 50K 31.5dB control 10 MUXOUT(R) 11 IN(R) 16 LP 24 VS 1.2nF 25 AGND Vref RB 19 CREF TREBLE-R 12 BIN(R) 13 BOUT(R)
SUPPLY
23
2.2F
22F 5.6nF 100nF 5.6K 100nF
2/17
+
SURR
+ MUTE 79dB CONTROL
SURR
30
LOUT
24 25 23
SCL SDA DIG GND
29
ROUT
27
LOUT
21 22 20
SCL SDA DIG GND
26
ROUT
MUTE 79dB CONTROL
D01AU1248
TDA7442 - TDA7442D
Table 2. Quick Reference Data
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Vout = 1Vrms (mode = OFF) Channel Separation f = 1KHz Treble Control (2db step) Bass Control (2dB step) Balance Control 1dB step (LCH, RCH) Mute Attenuation -14 -14 -79 100 Parameter Min. 7 2 0.01 106 90 +14 +14 0 0.1 Typ. 9 Max. 10.2 Unit V Vrms % dB dB dB dB dB dB
Table 3. Thermal Data
Symbol Rth j-pins Parameter Thermal Resistance Junction-pins Max. Value 85 Unit C/W
Table 4. Absolute Maximum Ratings
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 11 -10 to 70 -55 to +150 Unit V C C
Table 5. Electrical Characteristics Refer to the test circuit Tamb = 25C, VS = 9V, R L = 10K, Vin = 1Vrms; R G = 600, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.
Symbol SUPPLY VS IS SVR RIN VCL CRANGE AVMIN AVMAX ASTEP Gb BSTEP RB Supply Voltage Supply Current Ripple Rejection Input Resistance Clipping Level Control Range Min. Attenuation Max. Attenuation Step Resolution Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut 11.5 1 32 -1 31 THD = 0.3% LCH / RCH out, Mode = OFF 7 10 60 35 2 9 18 80 50 2.5 31.5 0 31.5 0.5 14.0 2 44 1 32 1 16.0 3 56 65 10.2 26 V mA dB K Vrms dB dB dB dB dB dB K Parameter Test Condition Min. Typ. Max. Unit
INPUT STAGE
BASS CONTROL
3/17
TDA7442 - TDA7442D
Table 5. Electrical Characteristics (continued) Refer to the test circuit Tamb = 25C, VS = 9V, R L = 10K, Vin = 1Vrms; R G = 600, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.
Symbol TREBLE CONTROL Gt TSTEP CRANGE SSTEP RPS10 RPS11 RPS12 RPS13 Control Range Step Resolution Control Range Step Resolution Phase Shifter 1: D1 = 0, D0 = 0 Phase Shifter 1: D1 = 0, D0 = 1 Phase Shifter 1: D1 = 1, D0 = 0 Phase Shifter 1: D1 = 1, D0 = 1 Max. Boost/cut +13.0 1 - 21 0.5 8.3 10 12.6 26.4 1 11.8 14.1 17.9 37.3 +14.0 2 +15.0 3 -6 1.5 15.2 18.3 23.3 48.85 dB dB dB dB K K K K Parameter Test Condition Min. Typ. Max. Unit
EFFECT CONTROL
SURROUND SOUND MATRIX PHASE
SURROUND SOUND MATRIX TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1 GOFF In-phase Gain (OFF) Mode OFF, Input signal of -1 0 1 dB
1kHz, 1.4 Vp-p, Rin Rout Lin
Lout LR In-phase Gain Difference (OFF) In-phase Gain (Music) Mode OFF, Input signal of 1kHz, 1.4 Vp-p Rin Rout, Lin Lout Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout), (Lin Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) - (Lin Lout) -1 0 7 1 dB dB
DGOFF GMUS
DGMUS
LR In-phase Gain Difference (Music)
0
dB
SPEAKER ATTENUATORS Crange SSTEP EA VDC AMUTE RVEA NO(OFF) NO(MUS) NO(PSEUDO) d SC VOCL ROUT Control Range Step Resolution Attenuation set error DC Steps Output Mute Condition Input Impedance Output Noise (OFF) Output Noise (Music) Output Noise (Pseudo Stereo) Distorsion Channel Separation Clipping Level Output Resistance d = 0.3% Output Mute, Flat BW = 20Hz to 20KHz Mode = Music , BW = 20Hz to 20KHz, Mode = Pseudo Stereo BW = 20Hz to 20KHz, Av = 0 ; Vin = 1Vrms 70 2 10 Av = 0 to -20dB Av = -20 to -79dB adjacent att. steps -0.5 -1.5 -3 -3 +70 21 79 1 0 0 0 100 30 4 5 30 30 0.01 90 2.5 30 50 0.1 39 1.5 1.5 2 3 dB dB dB dB mV dB K Vrms Vrms mVrms mVrms % dB Vrms
AUDIO OUTPUTS
4/17
TDA7442 - TDA7442D
Table 5. Electrical Characteristics (continued) Refer to the test circuit Tamb = 25C, VS = 9V, R L = 10K, Vin = 1Vrms; R G = 600, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.
Symbol VOUT d SC VOCL ROUT VOUT BUS INPUTS VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge IO = 1.6mA 3 -5 +5 0.4 1 V V A V MONITOR OUTPUTS Distorsion Channel Separation Clipping Level Output Resistance DC Voltage Level d = 0.3% Av = 0 ; Vin = 1Vrms 70 2 20 0.01 90 2.5 50 4.5 70 0.1 % dB Vrms V Parameter DC Voltage Level Test Condition Min. Typ. 3.8 Max. Unit V
5/17
TDA7442 - TDA7442D
3
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7442D and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data Validity As shown in fig. 5, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and Stop Conditions As shown in fig. 6 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 3.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master (P) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 3). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 3.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 5. Data Validity on the I2CBUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 6. Timing Diagram of I2CBUS
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 7. Acknowledge on the I2CBUS
SCL 1 2 3 7 8 9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
6/17
TDA7442 - TDA7442D
4
SOFTWARE SPECIFICATION
Interface Protocol The interface protocol comprises:

A start condition (S) A chip address byte, containing the TDA7442D A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB B DATA SUBADDRESS LSB ACK MSB DATA DATA 1 to DATA n LSB ACK P
D95AU226A
ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment 4.1 EXAMPLES 4.1.1 No Incremental Bus The TDA7442D receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these data concern the subaddress selected), a stop condition.
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB 0 X X SUBADDRESS LSB X D3 D2 D1 D0 ACK MSB DATA DATA LSB ACK P
D95AU306
4.1.2 Incremental Bus The TDA7442D receive a start conditions, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "1XXX1010" to "1XXX1111" of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concerns the subaddress sent plus one sent in the loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB 1 X X SUBADDRESS LSB X D3 D2 D1 D0 ACK MSB DATA DATA 1 to DATA n LSB ACK P
D95AU307
7/17
TDA7442 - TDA7442D
5
DATA BYTES
Address = 80(HEX) 5.1 Function Selection: The first byte (subaddress)
MSB D7 B B B B B B B B B B D6 X X X X X X X X X X D5 X X X X X X X X X X D4 X X X X X X X X X X D3 0 0 0 0 0 0 0 0 1 1 D2 0 0 0 0 1 1 1 1 0 0 D1 0 0 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 0 1 INPUT ATTENUATION SURROUND & OUT & EFFECT CONTROL PHASE RESISTOR BASS TREBLE SPEAKER ATTENUATION "L" SPEAKER ATTENUATION "R" NOT ALLOWED NOT ALLOWED INPUT MULTIPLEXER SUBADDRESS
B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1 Input Attenuation Selection
MSB D7 D6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 INPUT ATTENUATION 0.5 dB STEPS 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 4 dB STEPS 0 -4 -8 -12 -16 -20 -24 -28
INPUT ATTENUATION = 0 ~ -31.5dB
8/17
TDA7442 - TDA7442D
5.2 Surround Selection
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 BASS SELECTION MSB D7 X X X X X X X X X D6 X X X X X X X X X D5 X X X X X X X X X D4 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 D2 0 0 0 0 1 1 1 1 1 D1 0 0 1 1 0 0 1 1 1 LSB D0 0 1 0 1 0 1 0 1 1 BASS 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LSB D0 0 1 0 1 LSB D0 0 1 0 SURROUND MODE SIMULATED STEREO MUSIC OFF OUT VAR FIX EFFECT CONTROL -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 SURROUND PHASE RESISTOR PHASE SHIFT 1 (K) 12 14 18 37
PHASE RESISTOR SELECTION
9/17
TDA7442 - TDA7442D
5.2 Surround Selection (continued)
MSB D7 X X X X X X X MSB D7 X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 X 0 1 0 1 0 1 0 1 0 1 X X D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D6 X X X X X X X D5 X X X X X X X D4 1 1 1 1 1 1 1 D3 1 1 1 1 1 1 1 D2 1 1 1 0 0 0 0 D1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 LSB D0 0 1 0 1 0 1 0 1 BASS 2 dB STEPS 2 4 6 8 10 12 14 SPEAKER/ATT 1 dB STEPS 0 -1 -2 -3 -4 -5 -6 -7 8 dB STEPS 0 -8 -16 -24 -32 -40 -48 -56 -64 -72 MUTE
SPEAKER SELECTION
X = INDIFFERENT 0,1 SPEAKER ATTENUATION = 0dB ~ -79dB TREBLE SELECTION MSB D7 0 0 0 0 0 0 D6 0 0 0 0 1 1 D5 0 0 1 1 0 0 D4 0 1 0 1 0 1 D3 1 1 1 1 1 1 D2 1 1 1 1 1 1 D1 1 1 1 1 1 1 LSB D0 0 0 0 0 0 0 TREBLE 2 dB STEPS -14 -12 -10 -8 -6 -4
10/17
TDA7442 - TDA7442D
5.2 Surround Selection (continued)
MSB D7 0 0 1 1 1 1 1 1 1 1 MSB D7 X X X X X = INDIFFERENT 0,1 SPEAKER ATTENUATION = 0dB ~ -79dB TREBLE SELECTION MSB D7 D6 D5 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 0 0 INPUT SELECTION MSB D7 D6 D5 X X X X D6 D5 D4 D3 D2 0 0 1 1 D1 0 1 0 1 D6 1 1 1 1 1 1 0 0 0 0 D5 1 1 1 1 0 0 1 1 0 0 D4 0 1 1 0 1 0 1 0 1 0 D3 1 1 1 1 1 1 1 1 1 1 D2 1 1 1 1 1 1 1 1 1 1 D1 1 1 1 1 1 1 1 1 1 1 LSB D0 0 0 0 0 0 0 0 0 0 0 LSB D0 0 0 0 0 INPUT MULTIPLEXER IN2 IN3 IN4 IN1 TREBLE 2 dB STEPS -2 0 0 2 4 6 8 10 12 14
INPUT SELECTION
D4 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
D3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
LSB D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB D0 0 0 0 0
TREBLE 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14
D4
D3
D2 0 0 1 1
D1 0 1 0 1
INPUT MULTIPLEXER IN2 IN3 IN4 IN1
11/17
TDA7442 - TDA7442D
Table 6.
POWER ON RESET BASS TREBLE SURROUND & OUT CONTROL+ EFFECT CONTROL SPEAKER ATTENUATION L &R INPUT ATTENUATION INPUT 2dB 0dB OFF + FIX + MAX ATTENUATION MUTE MAX ATTENUATION IN1
Figure 8. PIN: TREBLE-L, TREBLE-R
VS 20A
Figure 11. PIN: CREF
VS 20K 42K 20A
25K
20K
D95AU336
GND
GND
Figure 12. PIN: SCL, SDA
D95AU309
20A
Figure 9. PIN: VOUT REF
VS 20A
GND
D94AU205
Figure 13. PIN: LP
VS
GND
D95AU233A
20A
10K GND
Figure 10. PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3,L-IN4, R-IN4,
VS 20A
GND
D95AU308
Figure 14. PIN: L-OUT, R-OUT
VS 20A
50K GND
VREF
D94AU200
GND
D95AU230
12/17
TDA7442 - TDA7442D
Figure 15. PIN: BASS-LI, BASS-RI
VS 20A
Figure 16. PIN: BASS-LO, BASS-RO
VS 20A
GND BASS-LO BASS-RO
45K : Bass
45K GND
D98AU949
BASS-LI,BASS-RI
D98AU950
13/17
TDA7442 - TDA7442D
Figure 17. SO-28 Mechanical Data & Package Dimensions
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
SO-28
8 (max.)
14/17
TDA7442 - TDA7442D
Figure 18. SDIP-32 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 B B1 C D E E1 e eA eB L 2.540 3.048 3.556 0.508 3.048 0.356 0.762 0.203 27.43 9.906 7.620 3.556 0.457 1.016 0.254 27.94 10.41 8.890 1.778 10.16 12.70 3.810 0.1 0.12 4.572 0.584 1.397 0.356 28.45 11.05 9.398 TYP. 3.759 MAX. 5.080 MIN. 0.14 0.020 0.12 0.014 0.03 0.008 1.08 0.39 0.3 0.14 0.018 0.04 0.01 1.1 0.409 0.35 0.070 0.400 0.500 0.15 0.18 0.023 0.055 0.014 1.12 0.433 0.37 TYP. 0.147 MAX. 0.2 inch
OUTLINE AND MECHANICAL DATA
SDIP-32 (Shrink Plastic Dip 32L)
E E1
A2
A
A1 L
B
B1
e
eA eB
D C
32
17
1
16
SDIP32M
0123183
15/17
TDA7442 - TDA7442D
Table 7. Revision History
Date January 2001 June 2004 Revision 1 2 First issue. Changed the Style-sheet in compliance to the new "Corporate Technical Pubblications Design Guide" Description of Changes
16/17
TDA7442 - TDA7442D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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